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Features
* * * * * * * * *
Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time - 120 ns Internal Program Control and Timer 16K bytes Boot Block With Lockout Fast Chip Erase Cycle Time - 10 seconds Byte-by-Byte Programming - 30 s/Byte Typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation - 25 mA Active Current - 50 A CMOS Standby Current * Typical 10,000 Write Cycles * Small Packaging - 8 x 8 mm CBGA - 8 x 14 mm V-TSOP
Description
The AT49BV/LV040 are 3-volt-only, 4-megabit Flash memories organized as 524,288 words of 8-bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 A. The device contains a user-enabled "boot block" protection feature. Two versions of the feature are available: the AT49BV/LV040 locates the boot block at lowest order addresses ("bottom boot"); the AT49BV/LV040T locates it at highest order addresses ("top boot").
4-Megabit (512K x 8) Single 2.7-volt Battery-VoltageTM Flash Memory AT49BV040 AT49BV040T AT49LV040 AT49LV040T AT49BV/LV040
(continued)
Pin Configurations
Pin Name A0 - A18 CE OE WE I/O0 - I/O7 Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs
A B 1
CBGA Top View
2 3 4 5 6 7
GND I/O6 VCC VCC I/O2 OE GND A17 I/O7 I/O4 NC NC I/O0 CE C A10 NC I/O5 NC I/O3 I/O1 A0 D A14 A13 A9 E A16 A11 WE NC F A15 A12 A8 NC A18 A5 A2 A7 A4 A1 NC NC A6 A3
PLCC Top View V - TSOP Top View (8 x 14 mm) or T - TSOP Top View (8 x 20 mm)
0679AX-A-9/97
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To allow for simple in-system reprogrammability, the AT49BV/LV040 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV040 is performed by erasing the entire 4 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 s. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new
access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
AT49BV/LV040 DATA INPUTS/OUTPUTS I/O7 - I/O0 8 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING 7FFFFH X DECODER MAIN MEMORY (496K BYTES) 03FFFH OPTIONAL BOOT BLOCK (16K BYTES) 00000H MAIN MEMORY (496K BYTES) 00000H OPTIONAL BOOT BLOCK (16K BYTES) 7C000H AT49BV/LV040T DATA INPUTS/OUTPUTS I/O7 - I/O0 8 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING 7FFFFH VCC GND OE WE CE
Y DECODER ADDRESS INPUTS
Device Operation
READ: The AT49BV/LV040 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 512K bytes memory array (or 496K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical "1". The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical "0") on a byte-bybyte basis. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert 2 "0"s to "1"s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the AT49BV/LV040 boot block is 00000H to 03FFFH while the address range of the AT49BV/LV040T boot block is 7C000H to 7FFFFH.
AT49BV/LV040
AT49BV/LV040
Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV/LV040 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TO G G L E B I T: I n a d d i t i o n t o D A T A p o l l i n g t h e AT49BV/LV040 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV/LV040 in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
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Command Definition (in Hex)
Command Sequence Read Chip Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit(2) Product ID Exit(2) Notes: 1. 2.
(1)
Bus Cycles 1 6 4 6 3 3 1
1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA F0
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55
5555 5555 5555 5555 5555
80 A0 80 90 F0
5555 Addr 5555
AA DIN AA
2AAA
55
5555
10
2AAA
55
5555
40
The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV040 and 7C000H to 7FFFFH for the AT49BV/LV040T. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground ............................ -0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ..................................-0.6V to + 13.5V
*NOTICE:
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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AT49BV/LV040
AT49BV/LV040
DC and AC Operating Range
AT49BV/LV040-12 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 2.7V to 3.6V/3.0V to 3.6V AT49BV/LV040-15 0C - 70C -40C - 85C 2.7V to 3.6V/3.0V to 3.6V AT49BV/LV040-20 0C - 70C -40C - 85C 2.7V to 3.6V/3.0V to 3.6V
Operating Modes
Mode Read Program
(2)
CE VIL VIL VIH X X X
OE VIL VIH X(1) X VIL VIH
WE VIH VIL X VIH X X
Ai Ai Ai X
I/O DOUT DIN High Z
Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification
High Z
Hardware
VIL
VIL
VIH
A1 - A18 = VIL, A9 = VH,(3) A0 = VIL A1 - A18 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A18 = VIL A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code (4)
Software(5) Notes: 1. 2. 3. 4. 5. X can be VIL or VIH. Refer to AC Programming Waveforms. VH = 12.0V 0.5V.
Manufacturer Code: 1FH Device Code: 13H (AT49BV/LV040), 12H (AT49BV/LV040T). See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH Note: 1. Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage In the erase mode, ICC is 50 mA. IOL = 2.1 mA IOH = -100 A; VCC = 3.0V 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA, VCC = 3.6V 12 Min Typ Max 10 10 50 1 25 0.8 Units A A A mA mA V V V V
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AC Read Characteristics
AT49BV/LV040-12 Symbol tACC tCE(1) tOE(2) tDF
(3)(4)
AT49BV/LV040-15 Min Max 150 150 0 0 0 70 40
AT49BV/LV040-20 Min Max 200 200 0 0 0 80 50 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever comes first
Min
Max 120 120
0 0 0
50 30
tOH
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. 2. 3. 4.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC . OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC . tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement level
Output test Load
tR, tF < 5 ns
Pin Capacitance
(f = 1 MHz, T = 25C) (1)
Typ CIN COUT
Note: 1.
Max 6 12
Units pF pF
Conditions VIN = 0V VOUT = 0V
4 8
This parameter is characterized and is not 100% tested.
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AT49BV/LV040
AT49BV/LV040
AC Byte Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 100 0 0 200 100 0 200 Max Units ns ns ns ns ns ns ns ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
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Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 100 100 0 200 200 10 Min Typ 30 Max 50 Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
Chip Erase Cycle Waveforms
Note:
OE must be high only when WE and CE are both low.
8
AT49BV/LV040
AT49BV/LV040
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: 1. 2. Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Write Recovery Time These parameters are characterized and not 100% tested. See tOE spec in AC Read Characteristics. 0 Min 0 10 Typ Max Units ns ns ns ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time
(2)
Min 0 10
Typ
Max
Units ns ns ns
150 0
ns ns
Notes: 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
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Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION (2)(3)(4) MODE
Boot Block Lockout Feature Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4) OR LOAD DATA AA TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE (4)
PAUSE 1 second
(2)
Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled.
Notes for software product identification: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A18 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 13H (AT49BV/LV040), 12H (AT49BV/LV040T).
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AT49BV/LV040
AT49BV/LV040
Ordering Information
tACC (ns) 150 ICC (mA) Active 25 Standby 0.05 Ordering Code AT49BV040-15CC AT49BV040-15JC AT49BV040-15TC AT49BV040-15VC AT49BV040-15CI AT49BV040-15JI AT49BV040-15TI AT49BV040-15VI AT49BV040-20CC AT49BV040-20JC AT49BV040-20TC AT49BV040-20VC AT49BV040-20CI AT49BV040-20JI AT49BV040-20TI AT49BV040-20VI AT49BV040T-15CC AT49BV040T-15JC AT49BV040T-15TC AT49BV040T-15VC AT49BV040T-15CI AT49BV040T-15JI AT49BV040T-15TI AT49BV040T-15VI AT49BV040T-20CC AT49BV040T-20JC AT49BV040T-20TC AT49BV040T-20VC AT49BV040T-20CI AT49BV040T-20JI AT49BV040T-20TI AT49BV040T-20VI Package 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V Operation Range Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
200
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
150
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
200
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
Package Type 32J 32T 32V 42C1 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 20 mm 32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 14 mm 42-Ball, Plastic Chip-Scale Ball Grid Array (CBGA) 8 x 8 mm
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Ordering Information
tACC (ns) 150 ICC (mA) Active 25 Standby 0.05 Ordering Code AT49LV040-15CC AT49LV040-15JC AT49LV040-15TC AT49LV040-15VC AT49LV040-15CI AT49LV040-15JI AT49LV040-15TI AT49LV040-15VI AT49LV040-20CC AT49LV040-20JC AT49LV040-20TC AT49LV040-20VC AT49LV040-20CI AT49LV040-20JI AT49LV040-20TI AT49LV040-20VI AT49LV040T-15CC AT49LV040T-15JC AT49LV040T-15TC AT49LV040T-15VC AT49LV040T-15CI AT49LV040T-15JI AT49LV040T-15TI AT49LV040T-15VI AT49LV040T-20CC AT49LV040T-20JC AT49LV040T-20TC AT49LV040T-20VC AT49LV040T-20CI AT49LV040T-20JI AT49LV040T-20TI AT49LV040T-20VI Package 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V 42C1 32J 32T 32V Operation Range Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
200
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
150
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
200
25
0.05
Commercial (0C to 70C)
25
0.05
Industrial (-40C to 85C)
Package Type 32J 32T 32V 42C1 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 20 mm 32-Lead, Plastic Thin Small Outline Package (TSOP) 8 x 14 mm 42-Ball, Plastic Chip-Scale Ball Grid Array (CBGA) 8 x 8 mm
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AT49BV/LV040

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